The present invention relates generally to semiconductor integrated circuits and, more particularly, to structures and methods involving dual gate oxide thicknesses on a single substrate.
A high-performance logic circuit with embedded memory devices needs two thicknesses of gate oxide: a thin gate oxide for the logic transistors, or logic MOSFETs, and the other a thick gate oxide for the memory device transistors and/or the high voltage transistors/MOSFETs. These gate oxide films are usually integrated on a wafer through a dual gate oxide (DGO) process.
Historically, dynamic random access memory (DRAM) and logic technologies have evolved along separate but parallel paths. For any particular lithography and power supply voltage level generation, the gate oxide thickness for the DRAM is limited by thin oxide reliability under the stress of voltage boosted word lines. For logic technology, on the other hand, gate oxide thickness is optimized around the need for high transconductance at lower internal operating voltages and therefore these gate oxides are generally thinner. Efforts to merge DRAM and logic onto a single chip to produce a xe2x80x9csystem on a chipxe2x80x9d or other high function DRAM thus must confront the choice of either compromising the gate oxide thickness for one or both device types, or assume the complexity and expense of two separately grown gate oxides. (See generally, S. Crowder et. al., xe2x80x9cTrade-offs in the Integration of High Performance Devices with Trench Capacitor DRAM,xe2x80x9d Int. Electron Devices Meeting (IEDM) Tech. Digest, Washington D.C., paper 2.6, 1997).
Recently, methods have been proposed which allow multiple gate oxide thicknesses to be produced under a single gate conductor by either implanting Ar+ or N+prior to oxidation. These techniques have been outlined in a paper by S. Crowder et al., entitled xe2x80x9cElectrical Characteristics and Reliability of Sub-3 nm Gate Oxides grown on Nitrogen Implanted Silicon Substrates,xe2x80x9d Int. Electron Devices Meeting (IEDM), Washington D.C., paper 2.6, 1997. Another paper on the topic has been presented by Y. Y. Chen et al., entitled xe2x80x9cPerformance and Reliability Assessment of Dual-Gate CMOS Devices with Gate Oxide Grown on Nitrogen Implanted Si Substrates,xe2x80x9d Int. Electron Device Meeting (IEDM), San Francisco, paper 26.4, 1997. Another paper on the subject has been provided by M. Togo et al., entitled xe2x80x9cMultiple-Thickness Gate Oxide and Dual-Gate Technologies for High Performance Logic-Embedded DRAMs,xe2x80x9d Int. Electron Device Meeting (IEDM), San Francisco, paper 13.1, 1998. And, still another paper on the subject has been provided by C. T. Liu et al., entitled xe2x80x9cMultiple Gate Oxide Thickness for 2-GHz System-on-a-Chip Technologies,xe2x80x9d Int. Electron Device Meeting (IEDM), San Francisco, paper 21.2, 1998.
Another method approach has been proposed which allows multiple gate oxide thickness to be produced under a single gate conductor by implanting O+ after gate deposition. (See generally, Y. C. King et al., xe2x80x9cSub-5 xcexcm Multiple-Thickness Gate Oxide Technology Using Oxygen Implantation,xe2x80x9d Int. Electron Device Meeting (IEDM), San Francisco, paper 21.2, 1998). Another method approach has been proposed for using different crystalline surface orientations. This approach is disclosed in application Ser. No. 09/386,185, by inventors W. Noble and L. Forbes, entitled xe2x80x9cMultiple Oxide Thickness for Merged Memory and Logic Applications,xe2x80x9d filed Aug. 31, 1999.
While these approaches decrease the required process complexity compared to the conventional process integration, they do require the addition of expensive process tools and steps. Clearly there remains a need to provide multiple gate oxide thicknesses on a single chip using existing process steps and little or no added complexity or costs.
In 1998 Oi et al introduced two processes of dual gate oxide formation. (See generally, Hideo Oi et al, xe2x80x9cDual Gate Oxide Process Integration for High Performance Embedded Memory Products,xe2x80x9d Extended Abstracts of the 1998 International Conference on Solid State Devices and Materials, p. 108-109, 1998). According to these processes, after trench isolation, the well and Vt adjust implantation were the same conditions as for a thin oxide (4 nm) logic baseline process. The single gate oxide wafers were oxidized only once for each oxide thickness (4 nm or 9 nm). Then two different DGO processes were tried. One included a Thick-Thin Process (TTDGO) where the wafer was oxidized for a 9 nm gate oxide first, and the oxide was removed, e.g. etched, from the intended thin-gate regions, and the wafer was reoxidized for a 4 nm gate. The other included a Thin-Thick Process (DGODP). Here, the wafer was oxidized for a 4 nm gate oxide first, followed by the first poly-Si deposition. Then, from the thick gate regions, this combined layer was removed, e.g. etched, and the wafer was reoxidized for a 9 nm gate oxide, followed by the second poly-Si deposition. It should be noted that both processes involve etching of oxide. This etching of the oxides has been shown to be highly detrimental to the reliable operation of these miniature devices.
For example, Cho et al. recently investigated the reliability of dual gate oxides produced from a two-step oxidation and wet etch process. (See generally, I. H. Cho et al., xe2x80x9cHighly Reliable Dual Gate Oxide Fabrication by Reducing Wet Etching Time and Re-Oxidation for Sub-Quarter Micron CMOS Devices,xe2x80x9d Extended Abstracts of the 1999 International conference on Solid State Devices and Materials, p. 174-175, 1999). Their research concluded that the degradation of the thick oxide was due to an increase of oxide surface micro-roughness and thinning at the edges induced by wet etching. They showed the Atomic Force Microscopy (AFM) images of two gate oxides after etching from a 10 nanometer (nm) thickness and from a 5.5 nm to 5 nm thickness. The corresponding rims (root mean square) roughness was 0.81 nm and 0.42 nm, respectively. The top surface of oxide was roughened during the wet etching. For longer time of etching, the rms roughness increased, and the charge to breakdown (Qbd) characteristics were degraded. A decrease of etched thickness of gate oxide significantly improved the oxide reliability, and showed the deep sub-quarter micron CMOS transistor without thinning the edges.
Further, in a recent article in Nature (published by the Macmillan Magazines Ltd.) Muller et al. emphasized two fundamental considerations on ultra-thin gate oxides. (See, D. A. Muller et al., xe2x80x9cThe Electronic Structure at the Atomic Scale of Ultra-Thin Gate Oxides,xe2x80x9d Nature, vol. 399, p. 753-761, 1999). First, the roughness of the interface must be controlled at an atomic scale. The leakage current through a 1 nm thick oxide increases by about a factor of 10 for every 0.1 nm increase in the rms roughness. This leakage current, in conjunction with the sub-threshold leakage, is the most important figure of merit in a MOSFET. Second, a single layer of silicon and oxygen has the incorrect topology to reproduce the local electronic structure of bulk silicon dioxide.
Thus, there is a need for structures and methods for ultra-thin dual gate oxide thicknesses which do not include an etching process. Furthermore, for giga-scale IC technology lower processing temperatures, using existing process steps with little or no added complexity, are highly desirable.
The present invention provides structures and methods for ultra-thin dual gate oxides on a single substrate which do not involve an etching step. Further, the ultra-thin dual gate oxides of the present invention utilize existing process steps with little or no added complexity and require lower processing temperatures.
According to one embodiment of the present invention, a method for forming gate oxides on a substrate is provided. The method includes forming a pair of gate oxides to a first thickness on the substrate. For example, in one embodiment, forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers. In one embodiment, forming the pair of gate oxides includes using a low-temperature oxidation method. A thin dielectric layer is then formed on one of the pair of gate oxides which is to remain as a thin gate oxide region for a logic device. The thin dielectric layer exhibits a high resistance to oxidation at high temperatures. In one embodiment, the thin dielectric layer includes a thin dielectric layer of silicon nitride (Si3N4) formed using jet vapor deposition (JVD). The other of the pair of gate oxides is then formed to a second thickness to serve as a thick gate oxide region for a memory device.
Another embodiment of the present invention includes the structure of a logic device and a memory device formed on a single substrate. The structure includes a first transistor which has a source and a drain region in the substrate separated by a channel region in the substrate. The first transistor includes a dielectric layer of a first thickness separating a gate from the channel region. The dielectric layer of the first thickness has a top layer which exhibits a high resistance to oxidation at high temperatures. The structure includes a second transistor which has a source and a drain region in the substrate separated by a channel region in the substrate. The second transistor includes a dielectric layer of second thickness separating a gate from the channel region. In one embodiment, the first transistor having a dielectric layer of a first thickness includes a dielectric layer having a thickness of less than 7 nanometers such that the first transistor is a transistor for the logic device. In one embodiment, the second transistor having a dielectric layer of second thickness includes a dielectric layer having a thickness of less than 12 nanometers and the second transistor is a transistor for the memory device.